The stringent power requirements of the chip stem from the product's power requirements. The rapid development of integrated circuits and the ever-increasing demand for consumer electronics, especially portable (mobile) electronic products, have made it impossible for designers to think about optimizing speed and area for battery-powered systems. The third important aspect - power consumption - is to extend battery life and electronics runtime. Many design choices can affect the power consumption of the system, from device selection to selection of state machine values ​​based on frequency of use.
1 basic concept of FPGA power consumption(1) The power consumption of power consumption is generally composed of two parts: static power consumption and dynamic power consumption. The static power consumption is mainly caused by the leakage current of the transistor, the leakage current from the source to the drain and the leakage current from the gate to the substrate. The dynamic power consumption is mainly caused by the charge and discharge of the capacitor. The main influence parameters are voltage and node. The capacitance and operating frequency can be expressed by equation (1) [1].
(2) Static power consumption Static power consumption is mainly caused by leakage current. Leakage current is the current that always exists when the chip is powered up, whether it is in the working state or in the static state, which is derived from the three poles of the transistor, as shown in Figure 1. It is divided into two parts, one part from the source to the drain leakage current ISD and the other part from the gate to substrate leakage current IG. The leakage current is inversely proportional to the channel length of the transistor and the thickness of the gate oxide [2].
Figure 1 Composition of static power consumption
The source-to-drain leakage current is the main cause of leakage. When the MOS transistor is turned off, the channel impedance is very large, but as long as the chip is powered, there is bound to be leakage current from the source to the drain. As the semiconductor process is more advanced, the transistor size is continuously reduced, and the channel length is gradually reduced, so that the channel impedance becomes smaller, so that the leakage current becomes larger and larger, and the source-to-drain leakage current increases with temperature. Increased exponentially.
(3) Dynamic power consumption Dynamic power consumption is mainly caused by capacitor charging and discharging. It is related to three parameters: node capacitance, operating frequency and core voltage, which are proportional to power consumption. As shown in equation (1), the larger the node capacitance, the higher the operating frequency, and the higher the core voltage, the higher the dynamic power consumption. The dynamic power consumption in the FPGA is mainly reflected in the power consumption of memory, internal logic, clock, and I/O. In a typical design, dynamic power consumption accounts for more than 90% of the overall system power consumption, so reducing dynamic power is a key factor in reducing overall system power consumption.
(4) Benefits of reduced power consumption 1 Low-power devices enable a lower-cost power supply system. In addition, a simpler power system means fewer components and a smaller PCB area, which also reduces costs [3].
2 Lower power consumption results in a lower junction temperature, so it can prevent thermal runaway, and can use less or no heat sink, such as cooling fan, heat sink, etc.
3 Reducing power consumption can lower the junction temperature, while lowering the junction temperature can increase system reliability. In addition, a smaller fan or no fan can reduce EMI [3].
4 Extend the life of the device. The device's operating temperature is reduced by 10 °C and the lifetime is extended by a factor of two.
Therefore, for FPGAs, the fundamental reason for reducing power consumption is to directly improve the performance and quality of the entire system, reduce the size, reduce the cost, and greatly promote the product.
(5) How to reduce FPGA power consumption
The main power consumption of FPGA is composed of static power and dynamic power. Decreasing the power consumption of FPGA is to reduce static power and dynamic power.
In addition to the process, static power has a lot to do with temperature. On the one hand, semiconductor companies need to use advanced low-power processes to design chips, reduce leakage current (that is, select low-power devices); on the other hand, reduce static power consumption by reducing temperature and structure.
FPGA dynamic power consumption is mainly reflected in the power consumption of memory, internal logic, clock, and I/O.
1 Selecting the appropriate I/O standard saves power. The I/O power consumption mainly comes from the external load capacitance connected to the output pin of the device, the impedance mode output drive circuit, and the charge and discharge current of the external matching network. You can choose a lower drive strength or a lower voltage standard. When system speed requires the use of high power I/O standards, the default state can be set to reduce power consumption. Some I/O standards require a pull-up resistor for proper operation, so if the default state of the I/O is high instead of low, the DC power through the termination resistor can be saved.
2 When the data on the bus is related to the register, chip select or clock enable logic is often used to control the enable of the register, and the logic is “data enabled†as early as possible to prevent the combination of the data bus and the clock enable register. Unnecessary conversions. Another option is to do this "data enable" on the board, not on the chip, to minimize the processor clock cycle. That is, use CPLD to offload simple tasks from the processor so that it stays in standby mode for a longer time [4].
3.2v12-30Ah Lithium Battery Cells
3.2v12-30Ah Lithium Battery Cells,3.2v12-30Ah Lithium Battery Cells price,3.2v12-30Ah Lithium Battery Cells product
Jiangsu Zhitai New Energy Technology Co.,Ltd , https://www.jszhitaienergy.com