Principle and method for reducing the on-resistance of high voltage MOSFET

The tech detail section features a series of product images and descriptions. The first image shows a domestic switch needle KG-300K with a 3.0mm head diameter, designed for normally open switches. Another image highlights an AVX tantalum capacitor, TPSD107K016R0100, known for its low resistance and original quality from 2011 onwards. A third image showcases a Shunuo varistor, emphasizing its ESD protection capabilities and comprehensive product range. The final slide displays a 1.5PF SOT23-6 low capacitance device with a 5V breakdown voltage and 6V SRV05 rating. Alongside the visual content, there is a detailed explanation about the on-resistance distribution in MOSFETs with varying voltage ratings. For a 30V MOSFET, the epitaxial layer contributes only 29% to the total on-resistance, while for a 600V MOSFET, it accounts for 96.5%. This suggests that for an 800V MOSFET, the epitaxial layer would dominate the on-resistance. Achieving high blocking voltage requires a thick, high-resistivity epitaxial layer, which inherently increases on-resistance—a key limitation in traditional high-voltage MOSFET designs. To reduce on-resistance, increasing die size is one approach, but it’s not commercially viable due to cost concerns. Introducing minority carrier conduction can lower the on-state voltage drop, but it comes at the expense of slower switching speeds and increased tail current, leading to higher switching losses. These trade-offs make it unsuitable for high-speed applications. The core challenge lies in balancing the need for low-doping, high-resistivity regions for blocking voltage with the requirement for high-doping, low-resistivity channels for conduction. One solution is to design a conductive channel with high doping and low resistivity, while ensuring the channel pinches off when the MOSFET is off, allowing the device's blocking voltage to rely solely on the low-doped N-epitaxial layer. This concept was realized with INFINEON’s COOLMOS technology introduced in 1988, featuring an integrated lateral electric field. Unlike conventional structures, this design embeds a vertical P region between N regions, creating a vertical electric field during turn-off. This allows the N-region to have higher doping than the epitaxial N-, enabling efficient blocking without sacrificing on-resistance. When VGS is below VTH, the PN junction is reverse-biased, forming a depletion layer that supports high blocking voltage. However, when VGS exceeds VTH, an N-type channel forms, allowing electrons to flow through the low-resistivity N-region, significantly reducing on-resistance compared to traditional MOSFETs. This separation of blocking voltage and on-resistance functions resolves the long-standing trade-off, converting surface PN junctions into buried ones. At the same N-doping concentration, this design enhances both blocking voltage and reduces resistance, making it a breakthrough in high-voltage power electronics.

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