The clock device design employs an I2C programmable fractional-phase locked loop (PLL) to meet high-performance timing needs, producing a frequency with zero parts-per-million (PPM) synthesis error. High-performance clock ICs feature multiple clock outputs capable of driving various subsystems like processors, FPGAs, data converters, and more in applications such as printers, scanners, and routers. These complex systems often require dynamic updates to the reference clock frequency to accommodate protocols like PCIe and Ethernet.
The clock IC operates as an I2C slave, requiring the host controller to configure its internal PLL logic. This control logic can be written to a microcontroller, acting as an I2C master to configure the clock IC's volatile memory and manage the PLL. Consequently, the system clock frequency can be dynamically updated via the on-board MCU-clock IC combo. Programmable microcontrollers offer control logic for high-performance clock ICs, simplifying the design and reducing costs by minimizing on-board components and traces.
In operation, Figure 1 illustrates the basic PLL architecture for a high-performance clock device. This design uses a scaling factor to synthesize the PLL output. The final output frequency is calculated as:
\[ f_{\text{out}} = \frac{f_{\text{ref}} \times \text{DIV}_N}{\text{DIV}_R \times \text{DIV}_O} \]
Where \( f_{\text{ref}} \) is the input reference crystal frequency (typically 8 MHz to 48 MHz), \( \text{DIV}_R \) is the prescaler, \( \text{DIV}_N \) is the fractional-N factor, and \( \text{DIV}_O \) is the post-divider.
The clock IC contains both volatile and non-volatile memory. The non-volatile memory is pre-written with the desired configuration at the factory and copies its contents to the volatile memory upon power-up. During this process, the PLL generates the required default clock output.
One key feature is runtime programming via the I2C interface, allowing users to instantly update the volatile memory contents for immediate changes. Users can also predefine multiple configurations in the non-volatile memory, selecting one via the Frequency Select (FS) pin, which is an external CMOS input. This pin allows the selection of different configurations stored in non-volatile memory, with the chosen configuration copied to volatile memory and output accordingly.
Microcontrollers play a crucial role in controlling the clock IC’s PLL. Figure 2 shows how the microcontroller interacts with the clock IC. The PLL block tunes the local oscillator frequency and generates a tuning voltage (Vtune), which adjusts based on the frequency band. The microcontroller communicates with the programmable divider through I2C, while the phase comparator ensures synchronization between the local oscillator and reference oscillator frequencies.
Dynamic frequency adjustments occur through the microcontroller’s ability to modify the prescaler and programmable divider values. For instance:
\[ \text{Step Size} = \left( \frac{\text{Local Oscillator Frequency}}{\text{Prescaler}} \right) \times \left( \frac{\text{Programmable Divider}}{\text{Reference Oscillator}} \right) \]
Table 1 lists several possible configurations.
In-system programming via the I2C interface allows designers to quickly iterate during system development. The microcontroller sends sequences of commands and data to the clock IC over the SCL and SDA pins. For example, in a scenario where the clock frequency must be a multiple of the sample rate, ranging between 155.52 MHz and 156.25 MHz, the microcontroller can adjust the PLL settings to accommodate these two frequencies.
Another feature is updating configurations via the FS pin. High-performance clock devices support multiple user profiles, with fast and slow switching options. Fast switching applies to output ON/OFF, crossover value changes, and output multiplexer (MUX) settings, while slow switching modifies PLL parameters. Despite the difference in speed, both modes ensure error-free output transitions.
External reset functionality brings the clock IC into low-power mode, placing outputs and I2C signals in a high-impedance state until the reset is canceled and initialization completes. This is particularly useful when restarting an application.
Voltage-controlled crystal oscillators (VCXOs) enable the clock frequency to track input data streams via analog feedback. Figure 5 shows an example where the clock IC integrates into a larger PLL, with an ASIC or SoC managing input tracking, error calculation, and PWM generation for frequency tuning.
Using microcontrollers with advanced IDE tools accelerates development. Devices like Programmable System-on-Chip (PSoC) simplify design complexity and reduce costs. For deeper insights into high-performance clock ICs, refer to resources like “Getting Started with 4-PLL Spread-Time Clock Generators†and “Design Best Practices for Spread-Time Clock Generators.â€
This combination of features makes high-performance clock ICs ideal for consumer, industrial, and networking applications, ensuring flexibility, precision, and adaptability in modern systems.
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