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Abstract: ZR36067 is a multimedia PCI bus controller introduced by ZORAN. The features, internal structure and pin functions of the ZR36076 are described in detail. An application example of ZR36067 in motion JPEG system is given. The working principle of the system is introduced in detail. Finally, the video interface connection method of ZR36067 and ZR36060 is given.
Keywords: multimedia controller PCI bus motion JPEG ZR36067
1 Overview
As a PCI adapter, the ZR36067 is designed for multimedia applications on PCI systems. It supports high rate code (compressed data stream) transfer between system memory and JPEG and MPEG processors. At the same time, the ZR36067 captures digital video (such as decompressed MJPEG, MPEG or video decoder output) and produces a scaled video window in the graphics display memory. Therefore, the ZR36067 can be used to control a large number of non-PCI multimedia devices through software. details as follows:
(1) Motion JPEG encoder/decoder - ZR36050+ ZR36016, ZR36060;
(2) an audio codec/decoder;
(3) MPEG and DVD decoders ZR36110 and ZR36700;
(4) I2C devices, such as video decoders, video encoders, etc.;
As a bus master, the ZR36067 can write data (such as JPEG compressed data) to or from the system memory and write digital video pixels into the graphics display memory. As a bus target, the ZR36067 maps host access to the microcontroller's 8-bit Auxiliary Bus.
The ZR36067 has a special "static transfer" port through which the main program can read and write digitized video information (RGB pixels) between the system memory and the video bus. This channel enables high speed transmission of still images to be compressed or decompressed by the JPEG chipset.
ZR36067 multimedia controller is mainly used for high quality video/audio capture/playback and PCI system editing board, multimedia/graphics subsystem using auxiliary PCI bus, PCI motherboard with multimedia function and JPEG/MPEG1 solution for PowerPC and Macintosh PCI system Wait.
   The main features of the ZR36067 are as follows:
â— Has a seamless interface with the PCI bus (compatible with PCI2.1);
â— has a minimum interface with JPEG decoder (ZR36060, ZR36050 + ZR36016), MPEG1 and DVD decoder (ZR36110, ZR36700), video decoder, video encoding;
â— It can realize bidirectional DMA transmission of compressed data, and the rate is close to 11Mbytes/s;
â— DMA transfer of video and mask information is possible;
â— Support compression and decompression of fast static images;
â— has a precise mask function in the slice pixel;
â— YUV-RGB converter can reduce quantization noise by error diffusion;
â— 15/16bit, 24 bit (compressed and uncompressed) RGB pixel format and YUV-4: 2:2 video output;
â— Hardware supports non-continuous JPEG code buffers;
â— Fault recovery with maximum bus execution time in video and code transmission;
â—Optional simulation of interlaced video display mode and single field display mode;
â— Available hardware supports simple and efficient frame grabbing;
â— with I2C bus interface;
â— Support plug and play;
â— 208-pin PQFP package;
â— Support subsystem ID and subsystem vendor ID.
â— can convert YUV4:2:2 digital video input into YUV4:2:2, RGB5-6-5, RGB5-5-5 or RGB8-8-8 (compressed or uncompressed) pixel formats;
In addition, the ZR36067 also supports CCIR601 digital video or square pixel format (compliant with NTSC or NTSC or PAL video standards) and other non-standard inputs.
2 internal structure
The ZR36067 internally includes two main data channels (video channel and code channel). Video information input through the PCI DMA burst mode is typically processed along the video channel and transferred to the graphics display memory. Its internal structure block diagram is shown in Figure 1.
The video front end of the ZR36067 samples the video bus in a programmable active field window defined by the video sync signal. Optional vertical, horizontal smooth scaling enables variable image size and variable PCI video data rates. The scaled video stream can be converted to a different RGB format. The converted pixels can be stored in a 256-byte video FIFO (64 32-bit double words) after compression. The stored video pixels can be read from the video FIFO and transferred to the graphics display memory.
The data flow direction of the bidirectional code channel depends on the operating mode. The code stream (MPEG or JPEG) is transferred in system memory and the internal code FIFO of the ZR36067 using the PCI DMA burst mode. The ZR36067 controls the transmission and addressing in both directions. The size of the code FIFO is 640 bytes (160 double words).
In JPEG compression mode, the ZR36067 fills the code FIFO through the encoder/decoder front end and transfers the code from the FIFO to the system memory field by field; in JPEG decompression mode, the code flow flows in the opposite direction, from system memory to ZR36067 The code FIFO, at this point the code/decoder front end can read the code FIFO contents byte by byte onto the code bus; in MPEG playback mode, the code stream is transferred from the system memory to the ZR36067 code FIFO. The code byte is read from the code FIFO onto the auxiliary bus; when the ZR36067 arbitrates the request of each process on the PCI bus, the ZR36067's video and code channels can operate simultaneously.
In addition to managing video and code channels, the ZR36067 also establishes a connection between the main CPU and peripherals (as auxiliary devices). In fact, using a dedicated handshake mechanism ("post office" mechanism), the main path of the main path of the ZR36067 internal register can also be mapped to the auxiliary bus to obtain indirect read and write operations to the auxiliary device.
Data transfer between the PCI interface and the video front end is achieved through the ZR36067's dedicated "static transfer" port. The main program can also transfer digital video (RGB pixels) from the system memory to the video bus using a special handshake protocol, and vice versa. In addition, the channel can also compress and decompress high-speed still video images through a JPEG encoder/decoder.
3 pin description
The ZR36067 is available in a 208-pin PQFP package. These 208 pins can be divided into the following categories:
(1) PCI interface (48 feet);
AD[31:0]: input/output, address/data multiplexed pin;
C/BE[3:0]: input/output, bus command/byte enable;
PAR: Input/output, parity of AD[31:0] and C/BE[3:0]:
FRAME: input/output, PCI cycle frame;
TRDY: input/output, PCI target ready signal;
IRDY: input/output, PCI master ready signal;
STOP: input/output, stop signal, used to indicate that the target requires the current bus master to stop the current transmission;
DEVSEL: Input/output, PCI device selection signal indicating that the target has decoded its address;
IDSEL: input, PCI initialization device selection signal, used for chip selection in the ZR36067 configuration space;
REQ: output, PCI request signal;
GNT: input, PCI enable signal;
PCICLK: input, PCI clock signal;
PCIRST: Input, PCI reset signal. When active low, all ZR36067 output pins are tri-stated. ZR36067 generally enters the power-on reset state on the rising edge of the PCI clock, and its minimum effective low duration is 3 PCI clocks.
INTA: Output, PCI interrupt signal.
(2) Digital video bus interface (32 feet)
Y[7:0]/R[7:0]: Input/Output, Brightness/Red Video Line. Also used to program the low byte of the subsystem vendor ID.
UV[7:0]/G[7:0]: Input/Output, Chroma/Green Video Line. Also used to program the low byte of the subsystem ID.
B[7:0]: input/output, blue video line;
VCLKx2: input, double frequency video bus clock;
VCLK: Input, digital video bus clock. When used as a quantizer for VCLKx2, it must be synchronized with VCLKx2;
HSYNC: input/output, digital video bus horizontal synchronization;
VSYNC: input/output, digital video bus vertical synchronization;
FI: input, digital video field counter (top/bottom);
PXEN: output, pixel enable output of ZR36016, low effective;
RTBSY: Input, ZR36016 strip memory overflow/underflow signal, low effective;
START: Output, ZR36016 starts processing output, high effective.
(3) Auxiliary bus interface (25 feet)
GCS[7:0]: output, chip select output of auxiliary bus device, low active;
GADR[2:0]: output, address output of the auxiliary bus device;
GDAT[7:0]: output, auxiliary data bus, can also be used for high byte programming of subsystem vendor ID;
GRD: output, read output of the auxiliary bus device, low effective;
GWR: output, write output of the auxiliary bus device, low effective;
GRDY: input, auxiliary equipment ready signal, high effective;
GWS: input, auxiliary equipment waits for status signal;
GIRQ[1:0]: Input, positive rising edge interrupt request input, usually from one to two auxiliary device buses.
(4) Encoder / decoder bus interface (11 feet)
CODE[7:0]: input/output, connected to the code bus of ZR36050;
CEND: input, field processing end signal from ZR36050, low effective;
CBUSY: Output, ZR36050 FIFO code busy signal.
(5) I2C bus interface (2 feet)
SDA: input/output, I2C bus data port;
SCL: I2C bus clock line.
(6) General purpose programmable input / output (8 feet)
GPIO[7:0]: General purpose input/output pin.
(7) Test pin (2 feet)
ENID: Input for IDD testing. Must be grounded during normal operation;
TEST: Input, test pin, only for test mode. It must be grounded during normal operation.
(8) Power and ground
GND: ground;
VDD: Positive power supply (5V)
4 Applications in the Motion JPEG system
Figure 2 is an application example of the Motion JPEG add-on device board that uses the ZR36067 and ZR36060 for interfacing. The ZR36067 supports four basic JPEG modes of operation: motion video compression, motion video decompression, still image compression, and still image decompression. The actual processing of these four modes of operation is now analyzed.
4.1 Motion Video Compression
When the YUV4:2:2 video signal and video sync signal are input to the video input of the ZR36060, it also transmits these signals to the ZR36067 video front end and video decoder (for display output on the TV monitor). Thereafter, ZR36067 The video compression will be selectively performed, and the video signal will be converted into an RGB signal, which is then transferred to the host PC memory by DMA. At the same time, the ZR36060 is also performing JPEG compression and streaming the JPEG code to the ZR36067 encoder/decoder front end, and then the ZR36067 DMA-based compressed video field signal is transmitted to the system memory buffer allocated by the host.
4.2 Motion Video Decompression
In motion video decompression, the ZR36067 uses DMA and passes the code stream from the system memory to the ZR36060 through the ZR36067 encoder/decoder front end. The ZR36060 decompresses the JPEG code and transmits the video signal to the video encoder for display on the TV monitor. Like the compression mode, when the ZR36060 outputs video information to the ZR36067 video front end for processing, the information is also transferred to the PC memory by DMA.
4.3 Still image compression
In the still image compression mode, the host will write image bitmap information to the ZR36067 pixel by pixel via the PCI bus. The ZR36067 then passes these pixels through their video bus port to the video input of the ZR36060. In this mode, the ZR36067 generates and drives the video sync signal required by the ZR36060. When the eight video lines are full, the ZR36060 begins raster-grid operation and compresses the data, while streaming the code to the ZR36067. As with motion video compression, code streams can also be streamed to host memory using DMA.
4.4 Still image decompression
The operation in the still image decompression mode is the same as the motion video decompression. The ZR36067 uses the DMA method to extract the code stream from the system memory, and uses ZR36060 to read the compressed data from the ZR36067. At the same time, the decompressed video information is sent after decoding. ZR36067's video port. Finally, the program reads the video information pixel by pixel from the program to the system memory.
It should be noted in the application that the still image decompression can also be implemented by configuring the ZR36067 in the motion video decompression mode and then transmitting the decompressed video information to a continuous buffer in the system memory. This method is often used because it has a faster speed than the still image decompression mode.
5 Video interface with ZR36060
Figure 3 shows the video interface connection between the ZR36067 and the ZR36060. For the four JPEG modes of operation of this circuit, the following issues should be noted in the design: In motion video compression, the YUV video and sync signals input to the ZR36067 and ZR36060 are from external video sources, such as SAA7110/7111; in motion decompression, The sync signal can be generated by the ZR36067 (in sync master mode) or a synchronizer connected to the video source. At this time, the video information of the ZR36067 transmitted from the ZR36060 video bus, the video bus and the synchronization signal of the external video source must also be floating; in the still image compression mode, since the video signal and the synchronization signal are from the ZR36067, The video bus and sync signal of the video decoder in Figure 2 must also be forced to float; in still image decompression, the sync signal comes from the ZR36067, so the compressed video information can be transferred from the ZR36060 to the ZR36067 video port. In this mode of operation, the video bus and sync signal of the external video source must also be left floating.
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