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Abstract: Aiming at the imaging and video processing front end of digital cameras, a design scheme based on TI DSP technology is presented. The functions and features of the image function unit CCD controller of the single-chip digital video decoder TVP5040 and the single-chip image processor TMS320DSC series DSP are introduced in detail, and the hardware connection and software implementation methods are given.Keywords: digital camera TVP5040 TMS320DSC series DSP CCD
At present, the demand rate of digital consumer electronics products is growing at an alarming rate. Among these products, imaging and video products have a large proportion. Among these imaging products, whether it is a digital camera or a camera phone with a built-in digital camera, or other digital imaging and video terminal products, imaging and video processing front ends need to work together.
Texas Instruments (TI) has followed up on advanced imaging applications for emerging consumer products and released the industry's highest performing digital signal processor (TMS320DSC family of DSP) solutions. This low-power, fully programmable DSP solution makes real-time video capabilities possible on imaging terminals. The TMS320DSC family of chips integrates two functions in a single device: the ultra-low-power TMS320C5000 for real-time media processing and one ARM7TDMI RISC processor for system control. Programmable hardware multimedia accelerators can perform concurrent processing to enhance dedicated imaging and video performance.
TI also offers a range of imaging and video processing front-end products that work seamlessly with the TMS320DSC family of DSPs. The TVP 5031, TVP5040 and TVP5145 enable users to convert analog video signals into digital data that can be processed by the TMS320DSC family of chips.
1 Digital camera imaging and video processing front end
The digital camera market is usually divided into high-end (more than 4 million pixels), mid-range (330, 2.1 million pixels) and low-end (one million grades below megapixels. For different markets, most manufacturers will follow CCD and CMOS). The difference is in different solutions, and the digital camera solution using the TMS320DSC series of DSPs can be balanced. From the entry-level products to the most advanced design of the entire camera system or other imaging products, the programmable ability of this series of DSP can be easily Implementation, this is one of its advantages. Second, the programmability of the imaging and video processing front-end TVP5031, TVP5040 and TVP5145 allows developers to upgrade or change the processing of the module's front-end through updated algorithms and standards.
   In general, the imaging and video processing front ends of digital cameras are mainly lens modules (including CCD sensors, lenses and motors) and analog front end circuits (AFE). The interface design of the imaging and video processing front end and the dedicated digital processor TMS320DSC described in this paper is shown in Figure 1.
The driving circuit and the timing generating device generate a clock signal required by the CCD or the CMOS. The function of the analog front end is to clamp and amplify the analog image signal output by the image sensor, and complete the A/D conversion, where the TVP5040 is used. The TMS320DSC series DSP includes image processing and timing control circuits. The timing generation can be controlled through the I/O interface. The vertical synchronization (VD) and horizontal synchronization (HD) signals can be correctly received by the CCD controller. After the relevant configuration, the DSP can accept the CCD raw data output by the TVP5040.
2 NTSC/PAL Digital Video Decoder TVP5040
As a high-quality single-chip digital video decoder, the TVP5040 can easily convert analog video signals into digital video. It includes two industry-leading 12-bit high-speed 2x oversampling A/D converters. Accepts standard NTSC/PAL composite video signal and S-Video signal input. The output format can be 8-bit, 10-bit, 16-bit or 20-bit 4:2:2 (YcbCr) sub-sampling format, or it can be 8-bit. Or standard output defined by 10 ITU-RBT, 656 (with embedded synchronization). The samples can be rectangular pixels or follow the ITU-RBT.601 protocol. The TVO5040 uses Texas Instruments' patented technology to capture weak, unstable signals and remove noise.
Its three-line complementary adaptive comb filter reduces the cross-effect of chromaticity and brightness. Video features such as hue, contrast, and saturation can be programmed with supported host ports and interface I2C, three parallel host interfaces (PHI), or VIP modes. The TVP5040 generates sync, blanking, field and latch signals, as well as digital video output. At the same time, it has advanced vertical blanking interval data recovery function, and the built-in FIFO can store up to 14 lines of teletext data.
TVP5040 mainly includes the following modules:
* Analog signal processor and A/D converter (AGC, AD);
*Y/C separation circuit (Luma/Chroma separation);
* chrominance processing;
*luminance processing;
* clock processing and power saving control;
* Output formatter (outputformatter);
* host port interface (interface);
*VBI Data Processor (VBI);
* Enhanced Macrovision detection (Macrovision detection).
   The module function is shown in Figure 2.
The TVP5040 is initialized and controlled by a set of internal registers that set all operating parameters. In order to properly set the parameters of the register, the host must download the microcode to the TVP5040 during power-on reset to allow the internal microprocessor of the TVP5040 to program the internal registers. Due to the large microcode, the TVP5040 provides different host port interfaces, including an I2C interface (I2C Interface), three parallel host interfaces (PHI Interface), and a video port interface (VIP Interface) for downloading and further configuration. The host interface is used to initialize the internal microprocessor, read and write status registers, and access fragmented VBI data. These interface modes are determined at power-on reset or when combined with GLCO, PALI, and FID pin resets.
The external controller communicates with the TVP5040 through a standard host port interface. The TVP5040 has an internal microprocessor and a connected 100K instruction RAM. The functions of the microprocessor control chip include PLL operation, AGC, synchronization, and register configuration. This programmable architecture allows the TVP5040 to take advantage of newer algorithms to improve performance. The microcode for the internal microprocessor is downloaded each time the power is turned on.
The sampling frequency that controls the number of pixels per line is different, depending on the video format and standard. The TVP5040 video port output format timing is shown in Figure 3. Others have timing diagrams for horizontal and vertical sync and field sync signals. Due to space limitations, they are not listed one by one.
3 TMS320DSC series DSP CCD controller
The image function unit CCD controller of the TMS320DSCX series DSP provides the necessary logic for CCD and CMOS image sensors, and provides excellent support for progressive and interlaced CCD or CMOS image sensors. The CCD controller can be programmed and has 20 registers to be set. It is controlled by TMS320DSCX and can support CCD up to 4096×4096 pixels. It has the following functions: CCD interface, digital clamp, timing generation and output formatting, as shown in Figure 4.
   The CCD controller collects and processes data of the CCD image sensor. The A/D conversion and timing generation required for the CCD is provided by an external chip. The CCD timing generator can provide HD/VD signals to external timing generation circuits, and can also receive and synchronize externally transmitted HD/VD signals. The CCD controller can handle up to 12-bit wide image data and can support point clocks up to 30MHz. Here, the TVP5040 is used to generate the timing required by the CCD controller, and the HD/VD, field ID, and pixel clock signals are transmitted.
A clamper samples the number of CCD black pixels and then subtracts the black level value from the value of each pixel. The user can set the position of the black level pixel through the register for the number of black pixels (8 or 16). Alternatively, the black value can be set to a constant.
The output formatter provides anti-aliasing filters, A-law compression, and horizontal and vertical downsampling. The anti-aliasing filter consists of a simple third-order filter. A-law table compression compresses data after 10 bits or more into 8 bits. Finally, a programmable downsampled template extracts N pixels from every 8 pixels.
The CCD controller provides two data channels. When passing through the channel, the pixel values ​​of 8, 10, and 12 bits are saved to the upper bits of a 16-bit SDRAM word, and the unused lower bits are filled with 0. When data is stored in SDRAM, 32 bits are saved each time, that is, 2 pixels, and the left pixel is saved to the lower 16 bits of 32 bits. In the data compression channel, the upper 10 bits of the image data are compressed into 8 bits, and then every 4 pixels are stored in a 32-bit word of the SDRAM.
4 DSP and TVP5040 hardware connection and software implementation
4.1 Hardware connection
Considering that the TMS320DSCX CCD controller can only receive 12-bit wide data, and the TVP5040 side decides to use the 10-bit YUV 4:2:2 video output format, the hardware connection of TMS320DSCX and TVP5040 is shown in Figure 5.
   Since the TVP5040 outputs 10-bit data, this design retains the highest bit, and the lower two bits are grounded or left floating. The TMS320DSC receives and synchronizes VD, HD and field signals from the TVP5040. When the image data is input to the TMS320DSC series DSP, it is latched on the rising and falling edges of the input point clock and can be set by the register DET. The CCD controller can store the data directly into the SDRAM, or compress the data into the SDRAM through the preview engine Burst compression unit.
The write signal (WEN) of the TVP5040 output is used to directly write data to the SDRAM from the CCD interface, which can be set by the EWEN bit. When the WEN signal is high read/write bit (RDWE), that is, the bit is "1", the image data is loaded into the SDRAM.
It should be noted that the TVP5040 must be connected to a 14.31818MHz crystal to maintain a normal operating frequency.
4.2 Software Implementation
First, the TVP5040 needs to be initialized, and the microcode is downloaded to the microprocessor through the I2C host port of the TVP5040.
Void TVP5040INIT(void)
{
resetTVP (); / / first reset the TVP5040
DELAYTIME; / / delay, download code requires timing stability
MicrocodeDown(); //Download microcode
RestartMicroprocessor();//After downloading, you need to restart the 5040 microprocessor
TimerWait(5); //Microprocessor restart needs to wait 5ms
PatchTVPRegister(); //The internal register is in the default state and needs to be reset.
}
Then you need to set up the CCD controller to get one frame of image data and send it to the SDRAM.
Void main()
{
TVP5040INIT (); / / initialize TVP5040
SdramInit(); //Initialize SDRAM
CCDCInit();//Initialize CCD controller
CCDCSetLinePerFrame();//Set the number of lines per frame of image
CCDCSetRawDataMode();//Set the width, polarity, position and direction of the internally generated timing signal
CCDCGetFrame();//Get one frame of image data and send it to SDRAM
}
   Then, the image data in the SDRAM can be processed, such as image compression or enhancement processing, which is beyond the scope of this article, and will not be described.
5 Conclusion
The above system has achieved very good results in the digital camera design. This high-performance, programmable, DSP-based solution has proven to make product development and application easier, laying the foundation for faster time to market.
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